The present invention relates to a method and apparatus for controlling conditional branch instructions for a pipeline type data processing apparatus.
FIG. 1 is a block diagram showing an example of a prior art pipeline type data processing apparatus. In FIG. 1, an instruction fetch unit 20 comprises an instruction buffer 300 for storing instructions read out of a memory 370, an instruction buffer control circuit or an instruction buffer controller 301 for controlling to write instructions from the memory 370 to the instruction buffer 300 and to read instructions from the instruction buffer 300, a selector 302 for selecting an instruction from the instruction buffer 300, and an instruction fetch control circuit or controller 303 for controlling the selector 302. A decoder unit 30 comprises an instruction register 304 for storing an instruction selected by the selector 302 and an instruction decoder 305 for decoding an instruction stored in the instruction register 304. An address calculating unit 40 comprises an address adder 306 for performing an address calculation. Reference numeral 307 designates an operand memory, and 308 an arithmetic unit. A branch judging unit 50 comprises a condition code store register 309 for storing a conditional code derived by the arithmetic unit 308, a branch condition store register 310 for storing a branch condition or an instruction mask bit of a conditional branch instruction or a branch on condition decoded by the instruction decoder 305, a condition comparing circuit or a condition comparator 311 for performing a condition comparison between the conditional branch instruction and contents stored in the condition code store register 309 and in the branch condition store register 310, and AND gates 313, 314 for determining whether or not a branch instructed by the condition branch instruction is taken on the basis of the comparison result obtained by the condition comparing circuit 311 and a conditional branch instruction executing command generated from the arithmetic unit 308 which indicates the execution of the conditional branch instruction. The outputs from the respective AND gates are signals indicating the judgement results, that is, whether a branch is taken or not.
A prior art pipeline type data processing apparatus will next be described with reference to a flowchart of a pipeline shown in FIG. 2.
In FIG. 2 the abscissa represents an executing cycle of a pipeline, where references 1 through .circle.15 are given for convenience so that each of sequential cycles can be referred to.
An example shown in FIG. 2 illustrates a case where instruction 2, instruction 3 and instruction 4, which do not cause a change in condition code, are executed subsequent to instruction 1 which causes a change in condition code, and next a conditional branch instruction 5 is executed.
After a determination has been made that a branch of the conditional branch instruction has been taken, instruction 6 and instruction 7, which are branch target destinations branched from the conditional branch instruction, are to be further executed.
The instruction 1 causing a change in condition code, fetched by the buffer 300, is selected by the selector 302 and input into the pipeline, that is, input into the register 304 at cycle 1, accesses the memory 307 at an address calculated by the address calculating circuit 306, executes an operation shown in the operand by the arithmetic unit 308 at cycle 5, obtains a condition code from the operation result, and sets the condition code in the register 309 at cycle 6.
The instruction 2 is input into the pipeline one cycle after the instruction 1 was, that is at cycle 2, and executes an operation to obtain a condition code at cycle 6. At this time, since the instruction 2 does not cause a change in condition code, the condition code set in the register 309 by the instruction 1 is not changed by the instruction 2.
Similarly, the instructions 3, 4 are input into the pipeline at cycles 3, 4, respectively, however, the condition code is not changed by either of them. The conditional branch instruction 5 is input into the pipeline at cycle 5. The conditional branch instruction 5 calculates at cycle 5 the address of a branch target instruction, accesses the memory 370 at the calculated branch target address through the instruction buffer control circuit 301, and reads from the memory 370 instruction 6 which is the branch target instruction at cycle 9. However, since a branch judgement has not been made, the branch target instruction is inhibited from being input into the pipeline. In consideration of a case where the branch is not taken, subsequent instructions are sequentially input into the pipeline at cycles 6, 7, . . . by the instruction fetch control circuit 303 before the branch judgement is given out. A branch condition defined by the conditional branch instruction 5 is decoded by the instruction decoder 305 at cycle 5, and the decoded branch condition is set in the register 310 at cycle 6. The condition code stored in the register 309 and the branch condition thus set in the register 310 are compared with each other by the condition comparing circuit 311, and the comparison result is output to the AND gates 313, 314. An execution command for executing the conditional branch instruction 5 is issued at cycle 9 by the arithmetic unit 308 and given to the AND gates 313, 314. A judgement is made to whether the branch is taken or not taken at cycle 9 from the execution command for the conditional branch instruction 5 and the comparison result from the condition comparing circuit 311. More specifically, when the execution command is output, it is judged that the branch is taken if coincidence of the condition codes is indicated between the output from the condition comparing circuit 311 and the branch condition, whereby the AND circuit 313, responsive to the judgement, outputs "1". The instruction 6, which is the branch target instruction, is then fetched from the buffer 300 by the control circuit 303 and the selector 302 and input into the pipeline at cycle .circle.10 , i.e., five cycles after the conditional branch instruction 5 has been input into the pipeline.
On the contrary, if the comparison result shows a discrepancy, the branch defined by the conditional branch instruction 5 is judged to be not-taken, and the AND gate 314 responsively outputs "1". As described above, a method of sequentially inputting instructions subsequent to the conditional branch instruction 5 into the pipeline is applied in consideration of the case where the branch is judged to be not-taken, so that a delay will not take place particularly with respect to the execution of instructions. When the branch is not taken, the branch target instructions 6, 7 read out of the memory 370 to be branched from the conditional branch instruction 5 are made invalid by the control circuit 303. On the contrary, when the branch is taken, subsequent instructions previously input into the pipeline are made invalid by the control circuit 303, thereby incurring no inconvenience.
In FIG. 2, in spite of setting the condition code of the instruction 1 at cycle 6, the branch taken judgement is made at cycle 9, that is, in response to the execution command for the conditional branch instruction 5, by the following reason.
If the branch taken judgement were made at cycle 6, an erroneous branch would be taken when the condition code of the instruction 1 cannot be set at cycle 6, for example, because the operand of the instruction 1 is missing in the memory 370.
For this reason, in the prior art the branch taken judgement is made at cycle 9 (an execution cycle of the conditional branch instruction) at which the condition code of the previous instruction has usually been definite. This type of apparatus, disclosed in JP-A-63-247833, is given as an example.
Generally, the performance of branch instruction processing decreases as a branch target instruction is fetched with a larger delay or as processing time for a judgement on taken/not-taken increases.
The above described prior art does not take account of the judgement on taken/not-taken for the case where a condition code has been definite earlier than the executing cycle of a conditional branch instruction. Therefore, the judgement on taken/not-taken is delayed until after execution of the executing cycle of the conditional branch instruction even though a condition code as well as a branch condition have already been definite, which leads to delay decoding and execution of branch target instructions and accordingly deteriorate the performance of branch processing.